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Pull requests: llvm/circt

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Pull requests list

[Synth] Add BooleanLogicOpInterface for and_inv
#10190 opened Apr 12, 2026 by uenoku Member Loading…
1
[SSP] Reimplement auxiliary dependences without symbols
#10189 opened Apr 12, 2026 by jopperm Contributor Loading…
1
[ci] Add integration test input to UBTI flows
#10188 opened Apr 12, 2026 by seldridge Member • Draft
2
[Synth][FunctionalReduction] support for inversion equivalences
#10181 opened Apr 11, 2026 by okekayode Loading…
1
9
[LLHD][SV] Unify the ProceduralRegion trait in CIRCTSupport
#10180 opened Apr 11, 2026 by fzi-hielscher Contributor Loading…
2
[Arc] Fix untracked op mutation in canonicalizer
#10176 opened Apr 11, 2026 by uenoku Member Loading…
don't emit redundant write_en = 0 for seq_mem
#10174 opened Apr 10, 2026 by Abhilekhgautam Loading…
1
2
[Sim] Implement the lowering logic from sim.proc.print to the SV dialect
#10172 opened Apr 10, 2026 by nanjo712 Contributor Loading…
16
[FIRRTL] InferDomains: support probes
#10167 opened Apr 9, 2026 by rwy7 Contributor Loading…
10
DRAFT: [3/2] [Moore] Lower class object access and virtual dispatch through LLVM memory
#10166 opened Apr 9, 2026 by Scheremo Contributor • Draft
[FIRRTL] Add lower-to-core lowering mode
#10162 opened Apr 9, 2026 by uenoku Member • Draft
13
[ESI][Runtime] Add SegmentedMessageData to support minimize copies ESI
#10160 opened Apr 9, 2026 by teqdruid Contributor Loading…
26
[FIRRTL][SpecializeOption] Allow specialization of non-existent option
#10158 opened Apr 8, 2026 by uenoku Member Loading…
[Moore][ImportVerilog] Model $cast with dyn_cast and success flag ImportVerilog
#10156 opened Apr 8, 2026 by sunhailong2001 Contributor • Draft
5
[FIRRTLToHW] Lower FIRRTL prints to Sim
#10153 opened Apr 8, 2026 by nanjo712 Contributor Loading…
2
[FIRRTLToHW] Lower firrtl.attach to new hw.attach and migrate SV-specific lowering logic to HWToSV.
#10138 opened Apr 6, 2026 by nanjo712 Contributor Loading…
6
[Synth][FunctionalReduction] Fix a SSA cycle
#10137 opened Apr 6, 2026 by uenoku Member Loading…
1
1
[FIRRTL] Fix getBitWidth to handle AnalogType
#10136 opened Apr 6, 2026 by unlsycn Member Loading…
[ci] Update UBTI to be run all tests
#10132 opened Apr 5, 2026 by seldridge Member • Draft
4
[2/2] [MooreToCore] Lower vtable method loads and vptr init
#10130 opened Apr 5, 2026 by Scheremo Contributor • Draft
1
[1/2] [MooreToCore] Lower symbolic vtables to LLVM globals
#10129 opened Apr 5, 2026 by Scheremo Contributor • Draft
10
[Moore][ImportVerilog][MooreToCore] Add DPI call semantics to Moore
#10126 opened Apr 5, 2026 by pscabot Contributor Loading…
15
[Verif] Preserve labeled assert/assume ops during canonicalization verif
#10114 opened Apr 3, 2026 by fabianschuiki Contributor Loading…
3
Do not merge: CI debugging
#10103 opened Apr 2, 2026 by fabianschuiki Contributor • Draft
2
Reject adding truncations for connections on inferwidths
#10100 opened Apr 1, 2026 by darthscsi Contributor Loading…
3
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